1. Field of the Invention
The present invention relates to an epitaxial wafer manufacturing method, an epitaxial wafer, a semiconductor device manufacturing method, and a semiconductor device, and more particularly, to a technique to manufacture an epitaxial wafer made of silicon carbide semiconductor.
2. Description of the Related Art
A lot of crystal defects and dislocations exist in an epitaxial wafer obtained by epitaxially growing silicon carbide (SiC) on a substrate. The crystal defects and dislocations are considered to make have adverse effects on the characteristics of SiC semiconductor devices. In particular, a basal plane dislocation (BPD) in an epitaxial growth layer expands to a stacking fault in a bipolar operation in the semiconductor device and a current is less likely to flow. Therefore, an on-state voltage of the semiconductor device increases and “bipolar degradation” occurs.
Several hundreds to several thousands of BPDs exist per square centimeter in the substrate. Most of the BPDs are converted into threading edge dislocations (TEDs) during epitaxial growth. However, a problem that the remaining BPDs penetrate up to at a surface and expand to be in triangular-shaped stacking faults occurs. The problem is being solved by improving epitaxial growth conditions to increase the efficiency of the conversion such that almost all of the BPDs are converted. However, in recent years, the expansion of a stacking fault in a bar shape has been reported, which causes a new problem for practical use of the SiC semiconductor device in which a bipolar operation occurs as recited in Non-Patent Literature (NPTL) 1.
In NPTL 1, a recombination electrons and holes in the semiconductor substrate is pointed as a factor which causes the expansion of the bar-shaped stacking fault. A scheme to increase the thickness of a buffer layer, which is epitaxially grown on a semiconductor substrate of a semiconductor device to prevent an excessively large number of holes from being injected into the semiconductor substrate, so as to suppress the recombination, is disclosed in NPTL 1. However, growing the thick buffer layer is not preferable, because costs increase owing to reduction of throughput of the process for epitaxial growth, and yield is reduced owing to increase of the defect density, and further, the resistance of the epitaxial wafer increases. Therefore, a technique to prevent the bar-shaped stacking fault is required, minimizing a thickness of the buffer layer.    [NPTL 1] J. J. Sumakeris et al., “Approaches to Stabilizing the Forward Voltage of Bipolar SiC Devices”, (USA), Materials Science Forum, Online Vol. 457-460, 2004, pp. 1113-1116